1. Field of the Invention
This invention relates to a structure and manufacturing method for dynamic random-access-memory (DRAM) capacitors, and, more particularly, to such a structure and manufacturing method for a stacked type capacitor as well as an improved version using a combination of stacked and trench type capacitors.
2. Description of Related Art
DRAM is a kind of volatile memory in which a digital signal is stored according to the charging state of the capacitor in each memory cell. FIG. 1 shows a circuit diagram of a DRAM cell, which includes a metal-oxide-semiconductor (MOS) transistor 11 with its gate connected to a word line (WL), one end of a source/drain region connected to a bit line (BL) while the other source/drain region connected to ground via a capacitor 12. The capacitor 12 can be regarded as the heart for the storage of digital signals in a DRAM cell. When the size of the charge stored in the capacitor 12 increases, the storage capacity for digital signals must also be increased. Furthermore, the signal read-out from the memory by amplification circuits during a read operation will be less affected by noise, for example, soft errors generated by a-particles will be greatly reduced.
Several conventional methods presently exist for increasing the charge storage capacity of the capacitor. For example, by increasing the surface area of the conducting layer in a capacitor or reducing the thickness of the dielectric layer in a capacitor, the quantity of charges capable of being stored in the capacitor can be increased. The stacked type capacitor as shown in FIG. 2 is one such example of a capacitor structure having an increased capacitor area.
FIG. 2 is a cross-sectional view showing a conventional stacked type DRAM capacitor structure. First, a semiconductor substrate 20 having a MOS transistor 22, a field oxide layer 26 and a conducting layer 27 is provided. The MOS transistor 22 includes a gate 23, source/drain regions 24 and spacers 25. Then, an insulating layer 28 is deposited, followed by etching of the insulating layer 28, to form contact openings above designated source/drain regions 24. Thereafter, a lower electrode layer 29, a dielectric layer 210 and an upper electrode layer 211 are sequentially formed above the contact window, providing a stacked type capacitor structure 212. The dielectric layer 210 can be a silicon nitride/silicon oxide (NO) composite layer or a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. The lower electrode layer 29 and the upper electrode layer 211 can each be a polysilicon layer. Finally, back-end processes such as the formation of a metallic contact window 213 and the laying of a passivation layer (not shown in FIG. 2) are performed to complete the remaining structural fabrication of the DRAM.
FIG. 3 is a cross-sectional view showing a second conventional stacked type DRAM capacitor structure. First, a semiconductor substrate 30 having a MOS transistor 32, a field oxide layer 36 and a conducting layer 37 is provided. The MOS transistor 32 includes a gate 33, source/drain regions 34 and spacers 35. Then, an insulating layer 38 is deposited, followed by the etching of the insulating layer 38, to form contact openings above designated source/drain regions 34. Thereafter, a lower electrode layer 39, a dielectric layer 310 and an upper electrode layer 311 are sequentially formed above the contact window to provide a stacked type capacitor structure 312. The dielectric layer 310 can be a silicon nitride/silicon oxide (NO) composite layer or a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. The lower electrode layer 39 and the upper electrode layer 311 can each be a polysilicon layer, and shaped such that the lower electrode layer 39 has an irregular rise and fall surface profile. Finally, back-end processes such as the formation of a metallic contact window 313 and the laying of passivation layer (not shown in FIG. 3) are performed to complete the remaining structural fabrication of the DRAM.
FIG. 4 is a cross-sectional view showing a third conventional stacked type DRAM capacitor structure. First, a semiconductor substrate 40 having a MOS transistor 42, a field oxide layer 46 and a conducting layer 47 is provided. The MOS transistor 42 includes a gate 43, source/drain regions 44 and spacers 45. Then, an insulating layer 48 is deposited, followed by the etching of the insulating layer 48, to form contact openings above designated source/drain regions 44. Thereafter, a lower electrode layer 49, a dielectric layer 410 and an upper electrode layer 411 are sequentially formed above the contact window, to provide a stacked type capacitor structure 412. The dielectric layer 410 can be a silicon nitride/silicon oxide (NO) composite layer or a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer. The lower electrode layer 49 and the upper electrode layer 411 can each be a polysilicon layer, and that the lower electrode layer 49 has an undulating surface profile serving to increase the surface area of the capacitor 412. Finally, back-end processes such as the formation of a metallic contact window 413 and the laying of passivation layer (not shown in FIG. 4) are performed to complete the remaining structural fabrication of the DRAM.
The aforementioned stacked type capacitor structures are the most common capacitor structures for DRAMs in use at present. These methods all rely on improving the surface morphology of capacitors. Although the increase in surface area of a capacitor obtained by such methods is capable of increasing its capacitance, the main drawback is that the amount of increase is quite limited, and is ineffective when applied to components of small dimensions.